problem about trdy in slavegreenspun.com : LUSENET : ece342 : One Thread
I just find out that the trdy in the slave device is positive edged. The conventional PCI trdy signal shown on the lab attachment is negative edged. Which convention should we use?? I programmed my PCI bridge to accept negative edged trdy signal and not the positive trdy signal! Which one is right?!
-- Roy Leung (firstname.lastname@example.org), March 22, 1999
PCI signals are sampled on the positive clock edge and asserted on the negative clock edge.
For the purpose of this lab you can assert signals after the positive clock edge.
-- Steven Caranci (email@example.com), March 23, 1999.