positive clock edge states

greenspun.com : LUSENET : ece342 : One Thread

Do we enact all changes onthe positive clock edges or do we follwo the pattern layout of the handout and invoike negative clock edge assertions?

-- timing (timing@timing.com), March 15, 1999

Answers

Everything is positive edge in the timing diagrams from the handout, so yes you should use positive edges. (Remember that there is always a delay from clock to output, so what you are seeing in the timing diagrams is signals changing *after* the positive edge. Depending on how slow they are, they may actually come out after the next falling edge, but they are still all activated/sensed on the rising edge.)

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), March 16, 1999.


Sorry, correction.

Sensing is done on the positive clock edge. *Activation* is done on the negative clock edge. For the purposes of this lab you can just use the positive clock edge for everything, state machines and outputs. (Though this is not true in general for PCI.)

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), March 16, 1999.


Moderation questions? read the FAQ