General Question about PCI labgreenspun.com : LUSENET : ece342 : One Thread
The followings are questions about the lab that I would like to ask:
1. Where can I find the PCI Slave file on this homepage?
2. When there is no transcation between the bridge device and slave device, should I raise AD, C/BE and other internal signals to high impedance? (I ask this because the internal signals that we design is not open collector.) If not, should we set to high (or low) when the lines not in used?
3. What should the bridge device do in Target Abort Sequence? (I cannot find infomation about it on the lab sheets.)
4. Since none of the control bits in the bridge device specifies the byte involved during the PCI transaction, how would the PCI bridge know what byte enable signal to put on the C/BE lines during each transfer?
5. Since the slave device contains two data register with different addresses [$200000] & [$280000], what address should the bridge put on the AD line if the PCI bridge device wants to write a 16 bit words to the slave device, so that the target know the transfer is going to be a 16-bit word?
-- Roy Leung (email@example.com), March 13, 1999
1: I will post a location today. You should, however, be able to start the bridge design without the Slave device. In fact, you should fully convince yourself that your bridge module works before connecting it to the slave. My advice would be for you put your bridge device in a vhdl file. Simulate and debug it as its own project. Then include this design and the slave in another vhdl file for the final simulations and debugging.
2: Since the signals are point to point you do not need to set them to tristate ('Z').
3: Abort the current transaction. There should be a waveform and small paragraph describing the Target Abort Sequence on the sheet attached to the lab handout proper.
4: Just transfer full 16-bit words.
5: The addresses specified in the handout for both the slave and the bridge are 68000 addresses. The slave will actually respond to any valid transaction on the PCI bus.
-- Steven Caranci (firstname.lastname@example.org), March 13, 1999.