memory as slave properties : LUSENET : ece342 : One Thread

In lieu of the DTACK and DMA question,

Are we to assume when we place address on bus $8XXCOUNT and assert ASnot, that some slave device (memory) will do it's thing and send back a DTACKnot or do we have to implement the slave in any way for this lab?

so the RAC is suspended and does not do anything during the time when the DMA controller has initiated BGACK?

therefore, the RAC is only used to initialize the values for three registers?

-- memory (, February 23, 1999


You should definately assume that the memory will respond properly, assuming that you have addressed it properly.

The only things that you are responsible for for this lab are:

1) a DMA bus master, and 
2) a control register bus slave.
The RAC is not necessarily suspended, but shouldn't do anything unless it has been properly addressed by some device (master) on the bus. As long as your DMA circuit (as bus master) doesn't address your registers, the RAC should remain inactive.

-- Steven Caranci (, February 23, 1999.

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