Lab 4 Wiring problemgreenspun.com : LUSENET : ece342 : One Thread
Do we have enough pins on the 7128 header to complete this lab? A previous posting (Re: lab 3 wiring problem) had said that there are 42 usable pins on the header and by my count we're using 49 for this lab.23 address lines 16 data lines 5 bus control lines (UDS, LDS, AS, DTACK, R/W) 3 bus arbitration lines (BR, BG, BGACK) 2 inputs for Clock and Reset. ----------------------- 49 pins.Am I missing something in the assignment, or is there a way of connecting to more pins on the Altera board.
-- Yoav Weinberg (firstname.lastname@example.org), February 18, 1999
There are also 3 dedicated inputs on the header. These could be used for Clock, Reset and on other input only signal.
That leaves 46 pins, but only 42 usable IOs. This can be solved in two ways. You can use some of the IOs that don't go to the cable and connect them using wires from the headers that surround the cpld on the Altera board. Or you may notice that not all of the Address bits need to be used as inputs to your design, but need only be driven with a constant value when your circuit is acting as bus driver. In this case you can use an external tri-state buffer to drive these signals.
-- Steven Caranci (email@example.com), February 18, 1999.