A few questions about lab 3greenspun.com : LUSENET : ece342 : One Thread
1. How long after /AS is asserted must /DTACK be asserted (or do timing restrictions even exist)?
2. If /UDS is asserted but /LDS is not, how should our device respond?
3. During a /CAS-before-/RAS refresh cycle, our lab handout indicates that A8-0 are don't care. However, the actual timing diagrams indicate that A7-0 are don't care. Which is correct?
4. Will the DATA lines be connected directly from the bus to the DRAM, or will they pass through some sort of buffer on the Altera board?
-- Steve Kushnir (firstname.lastname@example.org), February 01, 1999
There is no minimum requirement between /AS and /DTACK. There is some maximum after which it is assumed that no slave is ever going to respond (i.e. the BUS Error condition) but this is very large so unless your state machine is wrong you shouldn't be hitting it.
You assert /DTACK once you know data is available (read) or you don't need the CPU to drive the data any more (write). The CPU just spins (inserts wait cycles) until it sees /DTACK. For Lab2 you could provide data right away but for this lab you have to wait for the DRAM to successfully provide/latch the data.
If either /LDS on its own or both /UDS and /LDS are asserted then your controller can just respond normally (in the latter case you just ignore the high byte of data on a write and let the high byte float and return garbage on a read). If only /UDS is asserted (accessing the non-connected byte) we haven't specified what should happen. We're leaving it up to you to decide whether you ignore it or allow it to happen but don't take any meaningful action. Either way is fine but you should be able to justify your decision.
A8 is don't-care: typo in the datasheet. (The word description of the CAS-before-RAS cycle in the PDF indicates that there is an internal 9-bit counter so I would infer that A8 is not used. Most likely somebody cut-and-pasted the refresh diagram from another device which had one less pin.)
Since you have an /OE pin on the DRAM, the data pins do not need to go through the Altera device. (In fact there aren't enough pins to do this.)
-- Robin Grindley (email@example.com), February 01, 1999.