Question about refreshgreenspun.com : LUSENET : ece342 : One Thread
How many clock cycles does the refresh cycle take? Where can we find about this information?
-- Roy Leung (firstname.lastname@example.org), January 29, 1999
You will be doing the RAS/CAS signals synchronously using a state machine, so each cycle will be 100ns. If you look at the timing for refresh in the handout, the fastest you can do it is
0ns CLK 1 Assert CAS 100ns CLK 2 Assert RAS (and keep CAS asserted) 200ns CLK 3 De-assert CAS (and maybe RAS? check timing, see if this will work) 300ns CLK 4 De-assert RAS CLK ... Any wait states needed before IDLE?Check these numbers against the data sheets, and make sure that all timings meet the minimums.
-- Robin Grindley (email@example.com), January 30, 1999.
I don't think Robin answered the question that Roy was asking... (I'm not a TA, so someone please correct me if you think I'm wrong...)
From the timing diagram of the /CAS-before-/RAS Refresh Cycle (p2-13), RAS cannot be asserted again for 150ns [t(rc)] from the time /RAS is first asserted. Which, to me, means that since RAS can be asserted after 150ns (since last RAS), the RAM module will be ready to perform next R/W cycle -> refresh will be done within 150ns.
Also, provided that the state machine of the refresh is using the 100ns CLK, you *can* deassert both CAS and RAS at the same time... Since t(ras)=80ns (min), and t(chr)=30ns (min).
So, my refresh cycle looks like this:
0ns,assert CAS -> 100ns, assert RAS -> 200ns,deassert CAS&RAS -> 250ns, refresh complete -> 300+ns, start counter again, dram ready to R/W.
(again, I'm not a TA, this is just what I'm reading from the timing diagrams... If anyone disagrees, please post!)
-- Vincent Lo (firstname.lastname@example.org), February 01, 1999.